Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation
Yin, Haibing ; Park, Dong Sun ; Zhang, Xiao Yun
- Link zu diesem Datensatz
- https://d-nb.info/1090881444
- Titel
- Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation
- Art des Inhalts
- Teil eines Werks
- Verfassangaben
- by Haibing Yin, Dong Sun Park, Xiao Yun Zhang
- Autor(en)
-
- Yin, Haibing
- Park, Dong Sun
- Zhang, Xiao Yun
- Organisation(en)
-
- SpringerLink (Online service)
- Zeitliche Einordnung
- Erscheinungsdatum: 2013
- Umfang/Format
- Online-Ressource
- ISSN
18618219- DOI
- 10.1007/s11554-013-0341-6
- Online
- https://doi.org/10.1007/s11554-013-0341-6
- Sprache
- eng
- DDC-Klasse(n)
- Schlagwörter
-
- (lcsh)Computer science.
- (lcsh)Multimedia information systems.
- (lcsh)Computer graphics.
- (lcsh)Image processing.
- (lcsh)Pattern recognition.
- Computer Science.
- Image Processing and Computer Vision.
- Multimedia Information Systems.
- Computer Graphics.
- Pattern Recognition.
- Signal, Image and Speech Processing.
- Frühere/spätere Titel
-
- Enthalten in: Journal of real-time image processing
- Enthalten in: Journal of real-time image processing
- Enthalten in: Journal of real-time image processing
- Stand
- 12.02.2026 05:25
- Im Katalog seit
- 06.03.2026