„Multi core processor“

Suchergebnisse

161 Treffer

• Proceedings of the 4th Many-core Applications Research Community (MARC) Symposium
  Tröger, Peter ; Polze, Andreas 2012 Universität Potsdam
• OpenMP in the Era of Low Power Devices and Accelerators – 9th International Workshop on OpenMP, IWOMP 2013, Canberra, ACT, Australia, September 16-18, 2013. Proceedings
  Rendell, Alistair P. ; Chapman, Barbara ; Müller, Matthias S. 2013 Springer Berlin Heidelberg
• OpenMP in a Heterogeneous World – 8th International Workshop on OpenMP, IWOMP 2012, Rome, Italy, June 11-13, 2012. Proceedings
  Chapman, Barbara ; Massaioli, Federico ; Müller, Matthias S. ; Rorro, Marco 2012 Springer Berlin Heidelberg
• Performance Engineering for Exascale-Enabled Sparse Linear Algebra Building Blocks
  Kreutzer, Moritz ; Wellein, Gerhard ; Göddeke, Dominik 2018 FAU University Press
• A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
  Grudnitsky, Artjom ; Henkel, J. 2015 KIT-Bibliothek
• Publisher Correction: Cooperative, collaborative, coevolutionary multi-objective optimization on CPU-GPU multi-core
  Sun, Zhuoran ; Liu, Ying Ying ; Thulasiraman, Parimala
• Erratum to: Optimizing the Matrix Multiplication Using Strassen and Winograd Algorithms with Limited Recursions on Many-Core
  Khan, Ayaz ul Hassan ; Al-Mouhamed, Mayez ; Fatayer, Allam ; Mohammad, Nazeeruddin
• Automatic methods for distribution of data-parallel programs on multi-device heterogeneous platforms
  Moreń, Konrad ; Göhringer, Diana ; Cardoso, João M.P. 2024 Technische Universität Dresden
• Design and implementation of WCET analyses – including a case study on multi-core processors with shared buses
  Jacobs, Michael ; Hack, Sebastian 2021 Saarländische Universitäts- und Landesbibliothek
• Correctness of multi-core processors with operating system support
  Lutsyk, Petro ; Paul, Wolfgang Jakob 2018 Saarländische Universitäts- und Landesbibliothek
• VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design – 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers
  Burg, Andreas ; Coskun, Ayse ; Guthaus, Matthew R. ; Katkoori, Srinivas ; Reis, Ricardo 2013 Springer Berlin Heidelberg
• Adaptive multi-layer techniques for increased system dependability
  Bauer, Lars ; Henkel, Jörg ; Herkersdorf, Andreas ; Kochte, Michael Andreas ; Kühn, Johannes M. ; Rosenstiel, Wolfgang ; Schweizer, Thomas ; Wallentowitz, Stefan ; Wenzel, Volker ; Wild, Thomas ; Wunderlich, Hans-Joachim ; Zhang, Hongyan
• Modeling Cache Coherence to Expose Interference (Artifact)
  Sensfelder, Nathanaël ; Brunel, Julien ; Pagetti, Claire
• On How to Identify Cache Coherence: Case of the NXP QorIQ T4240
  Sensfelder, Nathanaël ; Brunel, Julien ; Pagetti, Claire 2020 Schloss Dagstuhl – Leibniz-Zentrum für Informatik
• Modeling Cache Coherence to Expose Interference
  Sensfelder, Nathanaël ; Brunel, Julien ; Pagetti, Claire 2019 Schloss Dagstuhl – Leibniz-Zentrum für Informatik
• Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors
  Nguyen, Viet Anh ; Hardy, Damien ; Puaut, Isabelle 2017 Schloss Dagstuhl – Leibniz-Zentrum für Informatik
• An empirical performance evaluation of SYCL on ARM multi-core processors
  Liang, Hanzheng ; Deng, Chencheng ; Zhang, Peng ; Fang, Jianbin ; Tang, Tao ; Huang, Chun
• Embedded Multi-Core Code Generation with Cross-Layer Parallelization
  Oey, Oliver ; Huebner, Michael ; Stripf, Timo ; Becker, Juergen 2024 Schloss Dagstuhl – Leibniz-Zentrum für Informatik
• A Graph based approach for Co-scheduling jobs on Multi-core computers
  Zhu, Huanzhou ; He, Ligang 2013 Schloss Dagstuhl – Leibniz-Zentrum für Informatik
• On the Determinism of Multi-core Processors
  Paun, Vladimir-Alexandru ; Monsuez, Bruno ; Baufreton, Philippe 2013 Schloss Dagstuhl – Leibniz-Zentrum für Informatik